Finite and Infinite Model Checking of Dual Transition Petri Net Models

[Extended Abstract] The formal verification of embedded systems is becoming a key research area due to the ever increasing design complexity involved in the modelling and validation of embedded systems. Traditional methods of validation, such as simulation and testing, are practically becoming an infeasible solution for large design models. Nowadays, only a small part of a real-life embedded system's state space can be explored by such traditional methods and, therefore, alternative ways of reasoning about the correctness of an embedded system are rapidly gaining popularity in hardware [1] and software [2] verification. The model checking [3] approach has been successfully applied to the verification of finite state concurrent systems, and is becoming of much interest in both industry and academia. This approach automatically verifies a system model, given a set of properties expressed in temporal logics [4], e.g. Computation Tree Logic (CTL) or Linear Temporal Logic (LTL) [5]. The specification of an embedded system may be well represented in Petri Net (PN) based models, which are capable of exploiting some desired features of the design, e.g. concurrency. The purpose of a model checking algorithm here, is to formally reason about behavioural properties of embedded systems described in terms of PN based models. An approach aimed to reduce the complexity of reachability trees in Petri nets, by means of BDDs, has been presented in [6, 7]. This verification methodology applies symbolic techniques to the encoding of the states in a concurrent formalism. PRES+ is another Petri net oriented model aimed to represent embedded systems, which has been applied to formal verification [8] of Timed CTL (TCTL) properties. In order to cope with verification, PRES+ models are transformed into Timed Automata. We had recently proposed a new PN based model which efficiently captures both control and data flow structure from a behavioural description of an embedded system [9]. This model, namely Dual Transition Petri Net (DTPN), is based on a PN structure and it is aimed to exploit the linkage between control and data flow in an embedded system specification, leading to better implementation results. In this work, we tackle the model checking of the recently introduced DTPN models [10] and extend this approach to also consider infinite state models. Our aim is to propose an homogeneous approach to undertake the problem of formal verification in an heterogeneous design model, e.g. embedded systems. One form of heterogeneity present in embedded systems is …